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Single-Phase Single Chip Graphics Core Power Supply
POWER MANAGEMENT Description
The SC473 is a single-phase chip, high-performance PWM controller designed to power advanced graphic cores. Onchip support is provided that includes slew-rate controlled VID transitions. The SC473 implements hysteretic control technology which provides the fastest possible transient response while avoiding the stability issues inherent to classical PWM controllers. Eliminating the sense resistors reduces costs and PCB area, plus increases system efficiency. Integrated SmartDriverTM technology initially turns on the high-side driver with `soft' drive to reduce ringing, EMI, and capacitive turn-on of the low side MOSFET, while also increasing overall efficiency. Hysteretic operation adaptively reduces the SC473 switching frequency at light loads. Combined with an automatic "powersave" mode which prevents negative current flow in the low-side FET, system efficiency is significantly enhanced during light loading conditions. A 5-bit DAC, accurate to 0.85%, sets the output voltage reference, and implements the voltage range required by the processor. The DAC slew rate is externally programmed to minimize transient currents and audible noise. True differential remote sensing provides accurate point-of-load regulation at the processor die. Other features include programmable soft-start, an open-drain PWRGD output, dual-level over-voltage and programmable over-current protection. The SC473 is available in a space-saving 4x4mm, 24-pin MLP package.
SC473
Features
Single-Phase Solution with Integrated Drivers Hysteretic Control for Fast Transient Response SmartDriverTM for reduced EMI True Differential Remote (die) Sensing VID Programmed Voltage Delayed Power Good Signal with Blanking Programmable Soft-Start and DAC Slew Control Programmable OCP Threshold Supports all Ceramic Decoupling Solutions 24-Pin MLP (4x4) Lead-Free Package RoHS and WEEE compliant
Applications
High Performance Graphics Embedded Applications
Updated - Aug 17, 2006
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9 8 7 6 5
R11
1
0 C5 1UF
9 8 7 6 5 2 9 8 7 6 5 1
TG +VGFX
1
L1 0.33UH +
3 2 1
PMON
C87
1
1
2
2
C85
R16
1 4 2 1
16.2K 22NF
Q2
D D
Q3
CR2 MBRS140L R29 C64
C88 330UF + 330UF 330UF
1
2
3 2 1
2 3 2 1
PGD C6 1NF
*10K
2
PMON
2
BST TG DRN BG V5 PMON
24 23 22 21 20 19
GND
CLSET VREF AGND ERROUT FBSS
HYS
25
1
CLSET 7 VREF 8 9 E_OUT 10 11 12
2
C63
1
10NF
1
C66 C89 *100PF C13 *100PF
1
1
2
C14
*100PF
R22 500K
2 E-RC 1 2 2 2 2 2
VREF 100PF
(c) 2006 Semtech Corp.
+VDC +V5S +V5R
Notes:
1 1 1 1 1 1
1) '*' in value = NO_POP
1
1
C86
C4 2 1UF
2 4 2
25V
C1 10UF
2 2
25V 25V
C2 10UF 10UF
2 2
25V 25V
C7 10UF 10UF
2
25V
C3 C12 10UF
*C10
*1uF
CR1 MBR0530
1
Q1
D
+V3.3S
2
BST
R2
1 2
1.15V @ 30A
5 1 3 1 4 2 6
C90 + C91 + 330UF
POWER MANAGEMENT Typical Application Circuit SC473
10K
2
PGD
DRN BG
1 4 2 1 2
1 1
C24
C16
*1NF
2 2
10uF
10uF
EN
2
R31 499 R13 10K R32 16.2K +VGFX
Note: All Grounds Tied together at output Caps.
R23
VID4 VID3 VID2 VID1 VID0
PGD EN RAMP CS+ CSFB+
VID4 VID3 VID2 VID1 VID0
1 2 3 4 5 6
VID4 VID3 VID2 VID1 VID0 HYS
SC473
U1
1
0 R34 499
18 17 16 RAMP 15 14 13
2
1
C65 100PF SS R102 10
1
C84
2
2
100PF
R17 130K
1 1
FB+ FBR103 10
C8 1NF R19 *8k 1
R18 130K
To Regulation Point
2 1
C9 *100PF
R20 90K
C11
1
2 2
*560PF VREF
SC473
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SC473
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltage (V5)
Condition
Min -0.3
Max 6.5 30 34 6 25 29 BST, +0.3 V5, +0.3 VCCA +0.3 28
Units V V V V V V V V V
o
Static BST to PGND BST to DRN DRN to PGND TG to PGND BG to PGND All Other Pins to PGND Thermal Resistance Junction to Ambient JESD51 Standard Method* Operating Junction Temperature Range Storage Temperature Range Peak IR Reflow (10-40sec) JA TJ TSTG TIRreflow Static Transient <100ns Transient <100ns
-0.3 -0.3 -0.3 -2 -5 DRN, -0.3 -0.3 -0.3
C/W
o
-40 -65
125 150 260
C C C
o
o
*Calculated from package in still air, mounted to 3" x 4.5", 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless otherwise specified, VccA = V5 = 5V, -40 < TJ < +125C.
Parameter Control / Driver Supply (V5) V5 Operating Range V5 UVLO
Condition
Min
Typ
Max
Units
4.5 Rising Hysteresis Falling EN = L0 4.25 50
5.0 4.4 150
5.5 4.5 250 10
V V mV A mA mA
V5 Current
In UVLO Operating (Static)
0.8 10
1.3 12
(c) 2006 Semtech Corp.
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SC473
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter Logic Inputs (EN, VID [4:0]) Enable Threshold VID [4:0] Threshold Input Impedance Reference (DAC, SS, VREF), (0 < TJ <85C) DAC Error + Internal Offset 1.15 - 0.85V 0.825V - 0.5V 0.475 - 0.375V DAC Sink/Source Ability SS Slew Current SS Discharge Threshold VREF Accuracy VREF Sink/Source Ability Remote Sense (FB+, FB-) Bandwidth(1) Error Amplifier (ERROUT) Gain Bandwidth(1) Current Sensing (CS+, CS-) CS+, CS- Input Bias Current Maximum Input Signal Zero-Crosssing Detector Threshold Powersave CS+ = CS- = 1.5V 50 -6 6 1 A mV mV 2 19 MHz 2 MHz 1.97 |1.5| 0.3V < DAC < 1.5V Start-up and Operating Discharge (SS = 0.5V) -0.85 -7 -14 |50| 102 15 50 2.00 400 2.03 120 138 +0.85 7 14 % mV mV A A mA mV V mA 0.8 0.45 40 2.0 0.55 V V k Condition Min Typ Max Units
(c) 2006 Semtech Corp.
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SC473
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter Current Sensing (CS+, CS-) (Cont.) Low-Pass Filter Corner Frequency(1) Current Limit Combined System (CLSET) CLSET = 1.2V, TG Low CL System Accuracy CLSET = 1.2V, TG High CLSET Input Bias Current Hysteresis Setting (HYS) HYS Input Bias Current HYS Gain (internal hysteresis setting relative to voltage applied at HYS pin) OVP and Internal Powergood Fixed Over-Voltage Protection Threshold Power Good Window Upper Threshold Power Good Window Lower Threshold Power Good Window Lower Hysteresis Powergood (PWRGD) Leakage On-Resistance Power Monitor CS+, CS- = 4mV CS+, CS- = 16mV 74 530 148 590 222 mV 650 PWRGD High Impedance VPG = 5V PWRGD = 0.1V 20 1 100 A FB Rising Relative DAC FB Falling Relative DAC FB Rising Relative DAC 1.65 +160 -360 30 1.7 +200 -300 50 1.75 +240 -240 70 V mV mV mV HYS = 1V 4 7 |1| 10 A % 16 32 |1| A 28 52 mV 50 80 125 kHz Condition Min Typ Max Units
PMON Output Voltage
VOUT = 1.2875 TJ = 25 oC
(c) 2006 Semtech Corp.
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SC473
POWER MANAGEMENT Electrical Characteristics (Cont.)
Parameter High-Side Driver (TG, BST, DRN) Peak Current(1)(2) RTTG_UP, DRN < 0.5V, 25C
G_UP
Condition
Min
Typ
Max
Units
1.75 4.1 3.48 0.9 0.76 0.42 0.34 17 9 30 10
2.0 5.8 5.8 1.3 1.3 0.6 0.6 22 12 45 20
2.25 7.5 9.24 1.7 1.7 0.78 1.01 27 15 60 30
A ns ns ns ns
RTTG_UP, DRN < 0.5V, -40 to 125C
G_UP
On-Resistance
RTG_UP DRN > 0.5V, 25C
TG_UP,,,,
RTTG_UP, DRN > 0.5V, -40 to 125C
G_UP
RTG_DN, at 25C
TG_DN
RTTG_DN, -40 to 125C
G_DN
Rise Time(1, 2) Fall Time(1, 2) Propagation Delay(1, 2) Shoot-thru Protection Delay(1) Lower-Side Driver (BG, V5, PGND) Peak Current(1, 2)
CTG = 3nF CTG = 3nF From Hysteretic Comparator Inputs to Driver Output
3.5 RBG_UP at 25C
BG_UP
4.0 1.3 1.3 0.5 0.5 7 3.5
4.5 1.7 2.1 0.65 0.86 9 4.5
A ns ns
0.9 0.76 0.35 0.28 5 2.5
On-Resistance
RBG_UP at -40 to 125C
BG_UP
RBG_DN at 25C
BG_DN
RBG_DN at -40 to 125C
BG_DN
Rise Time(1, 2) Fall Time(1, 2)
Notes: (1) Guaranteed by design. (2) TJ = 25C
CBG = 3nF CBG = 3nF
(c) 2006 Semtech Corp.
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SC473
POWER MANAGEMENT Pin Configuration
PMON DRN BST
Ordering Information
Device(2) Package MLP-4x4-24 Temp Range (TJ) -40C to +85C
BG
VID4 VID3 VID2 VID1 VID0 HYS
1 2 3 4 5 6
24 23 22 21 20 19
TG
V5
SC473MLTRT (1)(3)
18 17 16 15 14 13 PWRGD EN RAMP CS+ CSFB+
SC473EVB
EVALUATION BOARD
PGND PAD
7
CLSET
8
VREF
9 10 11 12
AGND ERROUT FBSS
SC473 Pin Out Diagram Top View
Notes: 1) Only available in tape and reel packaging. A reel contains 3000 devices. 2) This device is ESD sensitive. Use of standard ESD handling precautions is required. 3) Lead-free package compliant with J-STD-020B. Qualified to support maximum IR Reflow temperature of 260oC for 30 seconds. This product is fully WEEE and RoHS compliant.
Marking Information
yyww = Date Code (Example: 0550) xxxxx = Semtech Lot Number (Example: E9000) xxxxx = (Example: 1-100)
(c) 2006 Semtech Corp.
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SC473
POWER MANAGEMENT Pin Descriptions
SC473 Pin Configuration Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name VID4 VID3 VID2 VID1 VID0 HYS CLSET VREF AGND ERROUT FBSS FB+ CSCS+ RAMP EN PWRGD PMON V5 BG DRN TG BST Thermal Pad VID least significant bit Core comparator hysteresis - a resistor divider from VREF to AGND on this pin sets the hysteresis voltage Current limit set - a resistor divider from VREF to AGND on this pin sets the OCP threshold Internal reference voltage (2V) - bypass to AGND with a 1000pF NPO ceramic capacitor Quiet ground for analog control circuits Error amplifier compensation pin Remote GND sense - connect to VSS_Sense at the CPU socket Soft-start. The external NPO ceramic capacitor at this pin defines the soft-start ramp Remote die sense of core voltage - connect to VCC_Sense at the CPU socket Inverting input to Current-Sense amplifier Non-inverting input to Current-Sense amplifier An external R-C defines the internal slope ramp Enable control pin - active high Power good indicator, active high, open drain output Power Monitor output Input supply for both control circuits and gate drive. Connect to 5V and decouple with at least 1F ox X5R ceramic capacitance Output drive for the synchronous MOSFET Inductor switching node - connect to the junction of the switching and synchronous MOSEFETs Output drive for the switching MOSFET Bootstrap pin - a capacitor is connected between BST and DRN to develop the floating voltage for the switching MOSFET Power ground for driver - connect with at least two vias to the system GND plane VID most significant bit Pin Description
(c) 2006 Semtech Corp.
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SC473
POWER MANAGEMENT Block Diagram
VID [4:0] SS FBFB+ -
DAC
+ -
ERROUT
ERROR AMP
+ + -
HYSTERETIC COMPARATOR
I - limit
Hys_hi
CS+ CS-
+ -
CS
+
Hys_lo
CO
CURRENT SENSE AMP CL_hi
LP FILTER
-
CS
-
EN I - limit VID [4:0] DAC
REFERENCE & UVLO
+ -
VREF
CLSET
CL_lo
CO
+
PWRGD LOGIC
HYS_hi
3ms START UP TIME
PWRGD
HYS
HYS_lo
DRIVERS BST TG
CROSS CONDUCTION PROTECTION
EN
EN
DRN V5
CO
ZERO
CS
CROSSING
BG PGND
SC473
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SC473
POWER MANAGEMENT Applications Information
Introduction
The SC473 is a new generation of hysteretic converters which combines the best features of Semtech's hysteretic converter technology with the benefit of an error amplifier. The SC473 provides a complete solution to high performance graphics core requirements. In the SC473, the ripple for the hysteretic switching control is provided by DCR sensing. This provides several advantages over plain voltage-mode hysteretic converters, which switch on voltage ripple. * No current sense resistors are required resulting in higher converter efficiency * Full differential feedback of the output voltage from the CPU die is enabled * Stable with all-ceramic output Because the basic control is hysteretic, the SC473 provides the fastest possible transient response without switching at very high frequencies. This results in higher efficiency with less expensive parts because switching losses are reduced. The SC473 also provides a full range of features: * Graphics functions are implemented on-chip: * EN * PWRGD * VID programmable Output * Slew Rate Control * Power Monitor * A 2.00V voltage reference is provided * Separate hysteresis and current limit settings * A full suite of protection features is provided: * Over-current protection (OCP) * Fixed and DAC-referenced over-voltage protection (OVP) * Over-temperature protection (OTP) * Under-voltage detection via PWRGD All protection features are latching, and are reset either by recycling power or toggling the EN signal.
Theory of Operation
Voltage Regulation: Referring to the block diagram on the preceding page, the hysteretic comparator is the heart of the converter. The "FB+" input corresponds roughly to the CMPREF node of our older generations of IC; the "FB-" input is similar to CMP. To regulate, the comparator needs this information: * DAC (reference) voltage * Feedback voltage * Hysteresis voltage CMPREF receives the reference, voltage feedback and current information via current sense amplifier. The reference source is the DAC. The feedback voltage is received by the differential amplifier. A third amplifier, labeled the "Error Amplifier", multiplies the difference between the "ideal" voltage (DAC) and the actual voltage (FB+ minus FB-) for faster response. This signal is the reference for the hysteretic comparator. CMP has the ripple signal derived from the current sense inputs plus the hysteresis signal. The DC is stripped from the ripple signals by the combination of low-pass filter and summing amplifier. Current Limit Regulation: In Current Limit, the voltage hysteretic converter is overridden by the current limit hysteretic comparator, and the TG pulse is terminated when the output of the current sense amplifier reaches the CL_hi threshold and BG is terminated at the CL_lo threshold. These thresholds are set from the CLSET resistor divider: CL_hi = 0.33 * V(clset) CL_lo = 0.20 * V(clset) Current limit pulses continue until 32 pulses after the voltage droops to the PWRGD low threshold; then the controller latches off. This current limit algorithm is used in several generations of VCORE controllers and is extremely robust.
(c) 2006 Semtech Corp.
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SC473
POWER MANAGEMENT Applications Information (Cont.)
Start-Up and Soft-Off Sequences: For the SC473 cold start-up, V5 must rise above its undervoltage lockout (UVLO) threshold (4.4V typ.) The EN signal may go high either before UVLO or after (preferred). The DAC drives 120A (typical) into the soft-start capacitor on the SS pin. The SS pin and DAC rise slowly until the VID(4:0) When the voltage hits the lower PWRGD threshold, PWRGD goes high, and start-up is complete. In a normal shutdown, the EN signal is driven low, the TG and BG signals are driven low, tri-stating the power chains. An approximately 10 FET on the FB+ signal discharges Vcore slowly and prevents normal amounts of leakage from pulling Vcore high. The DAC is discharged to zero, but the power regulation circuitry is inactive, and PWRGD is low. DAC Description: A +/-0.85% 5-bit digital-to-analog converter (DAC) serves as the programmable reference source of the Core Comparator. Programming is accomplished by logic voltage levels applied to the DAC inputs. The VID code vs. the DAC output is shown in Table 1. The five voltage identification pins are used to support automatic selection of VOUT voltages. DAC Slew Rate Control: The DAC also has integrated slew-rate control with to charge and discharge the soft-start capacitor. All operating voltage transitions including soft-start use the 120A source to charge the soft-start capacitor. Power Supply Protection: The UVLO circuit consists of a comparator that monitors the input supply voltage level, V5. The SC473 is in UVLO mode when its supply voltage has not ramped above the upper threshold or dropped below the lower threshold. The output of the UVLO comparator turns on or off the internal bias, enables or disables the SC473 output, and initiates or resets the soft-start timer. The OVP circuit of SC473 monitors the processor core VOUT voltage for an over-voltage condition. If the FB voltage is 200mV greater than the DAC voltage (i.e., out of the powergood window), the SC473 will latch off and hold the lowside driver on permanently. Either the power or EN must be recycled to clear the latch. The latch is disabled
(c) 2006 Semtech Corp. 11
DRN
TH2 33k CS-
during soft-start and VID/DeeperSleep transitions. For safety, the latch is enabled if the FB voltage exceeds 1.7V even during VID transitions. The device will be disabled and latched off when the internal junction temperature reaches approximately 160C. Either the power or EN must be recycled to clear the latch. Power Monitor: The SC473 adds a power monitor feature to accurately predict the graphics CPU power consumption. The power monitor output depends on the current sensing methodology used. The following diagram and equation predict the ideal PMON output.
DC Voltage Between Two Terminals is: VDCR = I LOAD x RDCR
L1
+Vcc_core RDCR
I LOAD
Req = Parallel Combination of Resistors shown in the box
R28
Voltage Between these two terminals is Veq
C54
R24 18.2k
IR33
R33 5k CS+
VR33
R27 16.2k
R30
Power Monitor Implementation for SC473 (DCR Sense)
Req = (TH2 + R24)(R28 + R30 + R33) (TH2 + R24 + R28 + R30 + R33) Veq (VDCR x Req) (Req R27) IR33 Veq (R28 R30 R33) VR33 IR33 R33 PMON_Ideal V R33 Vcc_core 28.5
Similar exercise can be done for R-SENSE configuration as shown below:
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SC473
POWER MANAGEMENT Applications Information (Cont.)
ILOAD
L1
DC Sense Voltage VRCS = ILOAD x RCS +Vcc_core Rcs L-R
R25 100
R25 100 CS-
IR33
R33 5k
VR33
CS+
Power Monitor Implementation for SC473 (R Sense)
IR33 VDCR (R25 R25 R33) VR33 IR33 R33 PMON_Ideal V R33 Vcc_core 28.5
(c) 2006 Semtech Corp.
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SC473
POWER MANAGEMENT Applications Information (Cont.)
Component Manufacturer International Rectifier Fairchild Semiconductor Siliconix Infenion Technologies International Rectifier Fairchild Semiconductor Siliconix Infenion Technologies Various Various Vishay / Panasonic Various IRC, Panasonic Panasonic / NEC-TOKIN SPCAP Series or Part Number IRF7821, IRF6602, SSC3002S, Si4860DY,Si4410BDY
High Side MOSFET, HSFET
Low Side MOSFET, LSFET
Depends on Application
Boost Capacitor, Cbst Boost Diode, Dbst Output Inductor, L Decoupling Capacitors Current Sense Resistor Output Bulk Capacitors
X5R or better Schottky, 200mA or greater 0.2 H - 0.5H X5R or better ERJ-M1WTJ 330F, max ESR 6m
Company International Rectifier Panasonic IRC NEC/TOKIN Sanyo TDK Vishay/Dale Vishay/Siliconix
Contact Web: http://www.irf.com/product-info/ Phone: (310) 726-8000 Web: http://www.panasonic.com/pic/ecg/ Phone: (201) 348-7522 Web: http://www.irctt.com Phone: (888) 472-4376 Web: http://www.nec-tokinamerica.com/ Phone: (510) 324-4110 Web: http://www.sanyovideo.com/ Phone: (619) 661-6835 Web: http://www.component.tdk.com/components/components.html Phone: (847) 390-4373 Web: http://www.vishay.com/brands/dale Phone: (402) 564-3131 Web: http://www.vishay.com/brands/siliconix Phone: (800) 554-5565
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SC473
POWER MANAGEMENT Applications Information (Cont.)
Table 1. VID vs. VOUT Voltage
EN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X VOUT 1.1500V 1.1250V 1.1000V 1.0750V 1.0500V 1.0250V 1.0000V 0.9750V 0.9500V 0.9250V 0.9000V 0.8750V 0.8500V 0.8250V 0.8000V 0.7750V 0.7500V 0.7250V 0.7000V 0.6750V 0.6500V 0.6250V 0.6000V 0.5750V 0.5500V 0.5250V 0.5000V 0.4750V 0.4550V 0.4250V 0.4000V 0.3750V 0.0000V
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SC473
POWER MANAGEMENT Typical Characteristics
Nominal Load Regulation vs. Output Current
VOUT = 1.1500V Min-Max limits @ +/- 1% 1.1800
1.0000
Battery Load Regulation vs. Output Current
V OUT = 0.97500V Min-Max limits @ +/- 1%
1.1700
0.9900
1.1600 VOUT (V)
VOUT (V)
0.9800
1.1500
0.9700
1.1400
0.9600
1.1300
0.9500
1.1200 0.00
2.00 4.00
6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 26.00 28.00 30.00 32.00 34.00 Output Current (A) 19V 9V Min Nom Max
0.9400 0.00
2.00
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
20.00
22.00
24.00
Output Current (A) 19V 9V Min Nom Max
Figure 1 - Nominal Mode Line and Load Regulation
Figure 2 - Battery Mode Line and Load Regulation
Nominal Efficiency vs. Output Current
VOUT = 1.1500V 100.00%
100.00%
Battery Efficiency vs. Output Current
V OUT = 0.97500V
90.00%
90.00%
Efficiency (%)
80.00%
Efficiency (%)
80.00%
70.00%
70.00%
60.00%
60.00%
50.00% 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 26.00 28.00 30.00 32.00 34.00 Output Current (A) 19V 9V
50.00% 0.00
2.00
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
20.00
22.00
24.00
Output Current (A) 19V 9V
Figure 3 - Nominal Mode Efficiency v/s Output Current
Figure 4 - Battery Mode Efficiency v/s Output Current
Frequency vs. VIN
VOUT = 1.1500V @ 30A
60
PMON Error vs. Current
VOUT = 1.1500V
500000
50
400000
40 30 20 10 0 -10
Frequency (Hz)
300000
200000
100000
0 8.00
9.00
10.00
11.00
12.00
13.00
14.00 VIN (V) VIN
15.00
16.00
17.00
18.00
19.00
20.00
PMON Error (%)
-20 4.00
9.00
14.00
19.00 Iout (A) DCR SENSE
24.00
29.00
34.00
Figure 5 - Nominal Mode Frequency v/s Input Voltage
Figure 6 - Typical PMON Error v/s Output Current
*Above performance graphs correspond to Applications Schematic on page 2
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SC473
POWER MANAGEMENT Typical Characteristics
Figure 7 - Nominal Operation @ Iout = 30A
Figure 8 - Voltage Transition 0.95V to 1.15V
Figure 9 - Output Voltage with 24A load step
Figure 10 - Output Voltage with 24A dynamic load release
*Above performance graphs correspond to Applications Schematic on page 2
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SC473
POWER MANAGEMENT MLP-32 Outline Drawing - MLP 4x4-24
(c) 2006 Semtech Corp.
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SC473
POWER MANAGEMENT Land Pattern -- MLP-32 Land Pattern MLP 4x4-24
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804
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